1. Field of the Invention
The present invention relates to a semiconductor storage device that it is possible to facilitate miniaturization and refresh operation.
2. Related Art
There are various types of semiconductor storage devices such as DRAM, SRAM and flash memory. Among these devices, SRAM is capable of performing the read/write operations at a high speed. However, SRAM has more complicated circuit configuration than DRAM and requires six transistors for storing 1 bit data. Therefore, SRAM is not suitable for storing a large volume of data.
On the other hand, DRAM can be configured by only one capacitor and one transistor, so that DRAM facilitates miniaturization and is suitable for storing a large volume of data. However, in the case where DRAM is highly integrated, the area of a capacitor is also reduced, so that the quantity of electric charges storable in the capacitor is reduced so as to make it difficult to correctly determine the logic level of data.
As a method for solving the above described problems, there has been proposed a gain cell referred to as Asymmetric Three-Transistor Cell (ATC) for amplifying and reading out a small quantity of electric charges stored in minute capacitors (see STARC news issued on Jan. 15, 2005, Semiconductor Technology Academic Research Center (STARC), URL: http: //www.starc.or.jp).
In the gain cell disclosed in the above reference, PMOS transistors are used as the write transistor and NMOS transistors are used for the read-out transistor and the transistor for information amplification, respectively, so as to make the direction of gate leak paths to a storage node opposite to each other. Thereby, the final equilibrium level of potential in the memory is made to be an intermediate level between “1” and “0”, so that the data holding characteristic is improved against data destruction caused by the leak current without providing large capacitors, and electric power required for holding data can also be reduced.